In data communications, multiple communications devices exchange data through a communications interface, such as a parallel bus transmitting bits of data simultaneously along multiple data channels, and a serial bus transmitting data bit by bit sequentially over a single data channel. Modern communications equipment can be wired using both parallel and serial buses in various network architectures such as daisy chain and multi-drop basic topologies, or hybrid topologies combining characteristics of the basic topologies.
In a simple communications system, in which a host computer communicates data with multiple communications devices, serial buses are often used rather than parallel buses. Part of the reason for this is that a serial interface uses a smaller number of input/output terminals, and hence requires less packaging costs than a parallel one, and that in general, a serial bus can transmit data at a higher transfer rate than a parallel bus, thus meeting high-speed requirements for today's broadband network communications.
Currently, communications products with multiple serial data channels per interface are commercially available at relatively low cost. The multi-channel design enables serial data communications at a data transfer rate higher than that possible with a single data channel per interface, with one channel dedicated to reception from a data source and another to transmission to a data destination. Along with such high performance devices coming into common use, a greater need arises for ensuring proper data transfer in serial data communications at even higher data transfer rates, and consequently various methods have been proposed to provide high-speed, reliable serial data communications systems.
For example, one conventional method provides a communications system in which a host device communicates serial data to multiple peripheral devices connected in series to form a daisy chain network. According to this method, each peripheral device incorporates a processor to perform data transfer with upstream and downstream devices individually, enabling two interconnected nodes of the communications system to perform data transmission independently of the other nodes.
Designed to overcome problems encountered when a single host controls a daisy chain of multiple devices by providing short pulse “strobe” signals indicating when to capture data from a data line, this conventional technique eliminates the need for transmitting dedicated strobe signals to the multiple daisy-chained devices, resulting in reduced amounts of time and load required for the host device to access the peripheral devices. Such an effect is significant particularly where the system includes a large number of peripheral devices, requiring a greater number of strobe drivers, and a longer distance over which the host transmits data to the endmost node along the daisy chain.
Another conventional method provides a communications system in which a master device supplies data and clock signals to a daisy chain of multiple slave devices each equipped with a buffer circuit for receiving the supplied signals. According to this method, the buffer circuit captures data and clock signals to output synchronized data into the slave device, so that each slave device can correctly process the incoming data with the external clock signal even at higher data transfer rates.
Besides these conventional methods, several methods provide reliable data communications using a clock or strobe signal embedded in a data signal based on an encoding scheme, such as data strobe encoding, called DS-link, specified in IEEE 1394 or Institute of Electrical and Electronics Engineers high speed serial bus standard, or 8B/10B encoding used by Peripheral Component Interconnect Express (PCIe). Using embedded clocking to eliminate problems with skew between data and timing signals, these methods provide good synchronization between multiple communications devices, thereby enabling reliable high-speed data transfer in serial data communications systems.
FIG. 1 is a block diagram schematically illustrating a conventional serial data communications system 101 having a daisy chain topology.
As shown in FIG. 1, the communications system 101 includes a host computer 100 and multiple devices a1, a2, and a3 connected in series via a serial bus to form a daisy chain network, with the host computer 100 directly wired to the first device a1, the first device a1 to the second device a2, the second device a2 to the third device a3, and the third device a3 attached to a terminator 120 farthest from the host computer 100.
In the communications system 101, the host computer 100 connects to the first device a1 via a pair of data channels TDI0 and RDO0, one for transmission and the other for reception, as well as a clock channel CLK0 for providing a primary clock signal. Similarly, the first device a1 connects to the second device a2 via a pair of data channels TDI1 and RDO1, one for transmission and the other for reception, as well as a clock channel CLK1 for providing a buffered secondary clock signal, and the second device a2 connects to the third device a3 via a pair of data channels TDI21 and RDO21, one for transmission and the other for reception, as well as a clock channel CLK2 for providing a buffered tertiary clock signal. Each device has an internal processor that processes data input from the transmission channel TDI with the accompanying clock signal CLK for storage to an internal memory, and retrieves data from the internal memory for output to the reception line RDO0.
During operation, the host computer 100 submits a request for writing data to the multiple devices on the daisy chain, which travels along the transmission line TDI to propagate from one device to another sequentially throughout the communications system 101. Upon receiving the write request TDI0 from the host 100, the first device a1 retains the incoming data for processing in the internal processor before sending it to the downstream transmission channel TDI1 as well as to the internal memory, resulting in a period of delay longer than one cycle of the clock input CLK0 in executing and forwarding the write request TDI0 at the input stage. Similarly, the second device a2 involves an input delay of some cycles of the clock signal CLK1 in executing and forwarding the input request TDI1, and the third device a3 involves an input delay of some cycles of the clock signal CLK2 before executing and forwarding the input request TDI2.
Also, when the host computer 100 submits a request for reading data from the multiple devices on the daisy chain, each device retains desired data retrieved from the internal memory before sending it to the upstream reception channel RDO. As in the case of the writing operation, the result is that each device causes a period of output delay longer than one cycle of the clock input CLK in executing and forwarding the read request TDI at the output stage.
Naturally, such a processing delay is compounded as the transmitted data passes through an increasing number of interposed devices, resulting in varying amounts of latency (i.e., accumulated delay between when the host 100 submits a request to the transmission line TDI and when each device actually executes a requested service) for the multiple daisy-chained communications devices.
For example, given that each device requires an input delay of one clock cycle, the latency between the host 100 submitting a write request and each device actually writing the transmitted data to the internal memory increases depending on the relative positions of the host 100 and the particular device in the daisy chain network, measuring 1 clock cycle for the first device a1, 2 clock cycles for the second device a2, and 3 clock cycles for the third device a3.
Occasionally, the host computer 100 is required to time the execution of a read/write operation of each communication device to coordinate the overall operation of the communications system 101, for example, when the multiple devices perform a certain task in concert with each other. In such cases, the host computer 100 should transmit a read/write request to each particular device at a different time determined by the amount of latency that is inherent in the target device. However, determining a proper time at which to transmit a read/write request is difficult, since, as noted above, the amount of latency varies among the multiple daisy-chained devices, and each device typically has different amounts of latency for read and write operations.
One approach to cope with such variations in processing latency is to provide a strobe signal indicating to each communications device when to capture transmitted data, whereby the host can calculate the amount of inherent latency and determine the proper timing for request transmission accordingly. However, this approach is impractical considering that adding strobe channels dedicated to multiple devices results in higher costs and reduced data transfer rates of the communications system. Moreover, as for the conventional communications systems described above, unfortunately neither of them provides an effective solution to control the amount of latency for multiple communications devices in a daisy chain network.